FIELD OF THE INVENTION
The present invention relates to a microprocessor control signal timing circuit and, more particularly, this invention relates to a circuit for more accurately determining the arrival times of control signals supplied to microprocessors.
A problem arises in microprocessors when a relatively long time span passes from the arrival of a control signal which triggers an interrupt of the microprocessor until the output of a read command requesting the momentary counter reading of a first counter occurs. This is due to the interrupt delay time which may vary depending on the momentary load of the microprocessor. When such a delay occurs, the reading from the first counter no longer corresponds with the momentary counter reading at the point in time at which the control signal originally appeared. This occurs most frequently when successive control signals appear with a high repetition rate and may result in high rates of error.
It is thus an object of the present invention to provide a circuit which more accurately determines the arrival times of control signals in microprocessors to eliminate these errors.